A comprehensive project featuring an SPI-based Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) digital controller, verified within a RISC-V System-on-Chip (SoC) environment ...
Abstract: This paper introduces a 12-bit sub-radix successive approximation register (SAR) analog-to-digital converter (ADC) operating at $\mathbf{1 0 0 ~ MS/s}$. The design employs an optimized ...
Abstract: This paper proposes a novel Viterbi-Like successive cancellation (VL-SC) decoding algorithm for polar codes. The algorithm employs the bit log-likelihood-ratio as the “penalty value” within ...
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