IEEE

A 12-Bit 100MS/s SAR ADC with Sub-Radix and Optimize Digital Delay Path

Abstract: This paper introduces a 12-bit sub-radix successive approximation register (SAR) analog-to-digital converter (ADC) operating at $\mathbf{1 0 0 ~ MS/s}$. The design employs an optimized ...
IEEE

A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC

Abstract: This article presents a compact 13-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) designed to enhance energy efficiency under various comparator input ...